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| CXB1585N Fibre Channel Repeater Description The CXB1585N is a repeater IC with a built-in PLL clock recovery circuit for Fibre Channel 1.06Gbaud. This IC incorporates a port bypass circuit and is suitable for disk array and FC-AL HUB, etc. Features * Conforms to ANSI X3T11 Fibre Channel standard * Single 3.3V power supply * Low power consumption: 330mW (Typ.) * Low jitter * PLL lock detection circuit * Port bypass circuit * Small plastic package (24-pin SSOP) Applications * Fibre channel arbitrated loop 1.0625Gbaud HUB * Disk array Structure Bipolar silicon monolithic IC Pin Configuration 24 pin SSOP (Plastic) TEST1 VCCG TDSEL SDIN SDIN LKREF TDIN TDIN REFCLK 1 2 3 4 5 6 7 8 9 24 VEEG 23 VEEE 22 VCCE 21 SDOUT 20 SDOUT 19 TEST2 18 LKDT 17 TDOUT 16 TDOUT 15 VCCP 14 LPFPOS 13 LPFNEG VEET 10 VEEP 11 REXT 12 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96301-ST CXB1585N Block Diagram SDIN 1.063GBPS (ECL) 1.063GBPS (ECL) TDOUT TDOUT SDIN LPFPOS LPFNEG TDIN TDIN REXT 0 MUX SDOUT SDOUT 1.063GBPS (ECL) DFF Lock Det 1S 1.063GBPS (ECL) LKDT (TTL) Sig Det Phase Det 1 MUX 0S VCO LKREF (TTL) REFCLK 53.125MHZ (TTL) Freq Det 53.125MHZ / 20 -2- TDSEL (TTL) CXB1585N Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V) Item Supply voltage TTL DC input voltage ECL DC input voltage ECL differential input voltage TTL output current (High level) TTL output current (Low level) ECL output current Operating ambient temperature Storage temperature Symbol VCC VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg Min. -0.3 -0.5 VCC - 2 -2 -20 0 -30 -55 -65 Typ. Max. 4 5.5 VCC 2 0 20 0 70 150 Unit V V V V mA mA mA C C Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V) Item Supply voltage Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Unit V C -3- CXB1585N Pin Description Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description 1, 19 TEST1 TEST2 TTL input 3.3V TTL_IN Test pin. Connect to Vcc. VEEE VEET 2 VCCG Power supply 3.3V VCCG -- Positive power supply for internal logic gate. 3 TDSEL TTL input TTL level TTL_IN High; SDOUT outputs the SDIN retimed data. Low; SDOUT outputs TDIN data. VEEE VEET VCCE VCCG ECL_IN 4, 5 SDIN SDIN ECL input VCCE - 1.3V ECL level ECL_IN Serial data input. VEEE VEEG VCCG 6 LKREF TTL input TTL level TTL_IN Low; PLL takes the frequency from REFCLK. VEEE VEET -4- CXB1585N Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCE VCCG ECL_IN 7, 8 TDIN TDIN ECL input VCCE - 1.3V ECL level ECL_IN Serial data input. VEEE VEEG VCCG 9 REFCLK TTL input TTL level TTL_IN Reference clock input. This pin is used for the PLL to take the frequency. Input 53.125MHz to this pin. VEET VEET 10 11 VEET VEEP Power supply Power supply 0V 0V VCCP Negative power supply for REFCLK input. Negative power supply for internal PLL. 12 REXT External parts connection pin -- REXT Connects the resistor which determines the VCO center frequency. 4.7k resistor should be connected between this pin and VEEP. VEEP VCCP 13, 14 External LPFNEG parts LPFPOS connection pin LPF_A -- LPF_B Connects the external loop filter. VEEP -5- CXB1585N Pin No. 15 Symbol VCCP Type Power supply Typical pin I/O voltage 3.3V Equivalent circuit Description Positive power supply for PLL. VCCE 16, 17 TDOUT TDOUT ECL_OUT ECL output ECL level ECL_OUT Outputs the data input from TDIN via a buffer. VEEE VCCE 18 LKDT TTL output TTL_OUT TTL level VEEE PLL clock detection signal output.Outputs high level when PLL is locked to the serial data;Outputs low level when LKREF is in the low level or the serial data has no signal. The LKDT output may sporadically go high when the PLL starts to lock to the serial data. VCCE 20, 21 SDOUT SDOUT ECL_OUT ECL output ECL level ECL_OUT Outputs the serial data selected by TDSEL. VEEE 22 23 24 VCCE VEEE VEEG Power supply Power supply Power supply -- -- -- Positive power supply for input/output. Negative power supply for input/output. Negative power supply for internal logic gate. -6- CXB1585N Electrical Characteristics DC Characteristics Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current TTL high level output voltage TTL low level output voltage ECL high level input voltage ECL low level input voltage ECL differential input voltage ECL high level output voltage ECL low level output voltage ECL output amplitude Current consumption Power consumption Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T VIH_E VIL_E VIS_E VOH_E VOL_E VOS_E ICC PD VCC - 1.17 VCC - 1.81 200 VCC - 1.05 VCC - 1.81 650 101 333 127 438 -400 2.2 0.5 VCC - 0.88 VCC - 1.48 1000 VCC - 0.81 VCC - 1.55 Min. 2 0 Typ. (under the recommended operating conditions) Max. 5.5 0.8 20 Unit V V A A V V V V mV V V mV mA mW AC coupling input 50 terminated to Vcc - 2V 50 terminated to Vcc - 2V 50 terminated to Vcc - 2V Output pins open Output pins open VIH = VCC VIL = 0 IOH = -0.4mA IOL = 2mA Conditions AC Characteristics Item REFCLK rise time REFCLK fall time TTL output rise time TTL output fall time ECL output rise time ECL output fall time SDIN data rate REFCKL cycle tolerance Jitter tolerance Deterministic jitter Random jitter Bit sync time Frequency take-in time Symbol Tir_RC Tif_RC Tor_T Tof_T Tor_E Tof_E SDIN Ttol_RC JT Dj RJ Tbs Tfa 0.02 0.18 1000 -100 1062.5 0 Min. Typ. (under the recommended operating conditions) Max. 4.8 4.8 3.5 3.5 400 400 1100 100 0.7 0.07 0.23 2500 500 Unit ns ns ns ns ps ps Mbaud ppm Ul Ul Ul bit s K28.5 serial data Serial data FC Idle Pattern Loop Damping Capacitor C1 = 0.01F Refer to the SDIN cycle Conditions 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF 20 to 80%, CL 2pF 20 to 80%, CL 2pF -7- CXB1585N Electrical Characteristics Measurement Circuit (See "Fig. 3 Power Supply Circuit" regarding the power supply.) II_T Measurement device TTL_IN VI_T TTL_OUT Io_T Vo_T (a) TTL I/O DC characteristics measurement circuit Pulse generator Measurement device TTL_IN TTL_OUT CL Probe Oscilloscope CL = 10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E Measurement device ECL_IN ECL_OUT 50 VCCE - 2V A VI_TE V VO_E (c) ECL I/O DC characteristics measurement circuit VCCE - 2V 50 Pulse generator 50 50 Transmission Line VCCE - 2V VCCE - 2V CL 2pF (input capacitance of the measurement equipment and floating capacitance) VCCE - 2V 50 Oscilloscope 50 Measurement device ECL_IN ECL_IN ECL_OUT ECL_OUT (d) ECL I/O AC characteristics measurement circuit 26.5625MHz Measurement device VCCE - 2V SDIN 50 SOUT SOUT 1.0625GBPS 50 VCCE - 2V Triger Pulse generator 1.0625GBPS Oscilloscope SDIN (e) Jitter characteristics measurement circuit -8- CXB1585N Notes on Operation 1. Clock synthesizer (PLL) The CXB1585N has a PLL-based clock recovery circuit for recovering the clock from the serial data. This clock recovery circuit requires an external loop filter and an external resistor which determines the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the IC pins (Pins 12, 13 and 14) which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. In addition, capacitor C1 should have a small temperature coefficient to reduce the temperature dependence of the VCO oscillation frequency. CXB1585N 11 VEEP LPFPOS 14 C1 12 R1 REXT LPFNEG 13 R1: 4.7k C1: 0.01F Fig. 1. External Part Circuit and Recommended Constants -9- CXB1585N 2. ECL input circuit The ECL differential input pins are biased to VBB (VCC - 1.3V) via an 18k resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 18k 18k 160 3.3V ECL output buffer 160 ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer VCC VCC = GND, VEE = -4.5V 220k 330pF 18k VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 330pF 330 ECL100K output buffer 330 VEE 18k ECL differential input buffer (b) ECL differential signal from ECL 100K output buffer VCC VCC = 3.3V, VEE = GND 220k 330pF 50 TRANS. LINE 330pF 50 50 VTT (VCC - 2V) ECL differential input buffer 18k 18k VBB (VCC - 1.3V) (c) ECL differential signal from 50 transmission line VCC VCC = 3.3V, VEE = GND 220k 330pF 50 TRANS. LINE 18k VBB (VCC - 1.3V) 50 VTT (VCC - 2V) 330pF 18k ECL differential input buffer (d) ECL single signal from 50 transmission line Fig. 2. ECL Input Circuits - 10 - CXB1585N 3. Power supply VCCT VCCG VCCP 3.3V 22F 0.1F 22F 0.1F 22F 0.1F VEET VEEG VEEP Fig. 3. Power Supply Circuit 4. SDIN, SDIN inputs Normally, the VCO performs frequency comparison with the SDIN and SDIN serial data. When there is no input to SDIN and SDIN, frequency comparison is executed with REFCLK. However, the frequency may not be compared to REFCLK if the noise and others are detected as a signal for no signal state because the both phases of the ECL differential inputs are internally biased to VBB shown below. As countermeasure to this, connect either of the differential inputs to VCC via a resistor to generate the voltage difference for the both phases. VCC 220k 330pF 50 TRANS. LINE 330pF 50 50 ECL differential input buffer VTT (VCC - 2V) 18k 18k VBB (VCC - 1.3V) ECL differential signal from 50 transmission line Fig. 4. SDIN and SDIN Input Example - 11 - CXB1585N Example of Representative Characteristics Jitter Transfer 5 0 Jitter Transfer [dB] -5 -10 C1 = 0.01F, R1 = 4.7k, Ta = 27C Pattern: Fibre Channel ldle Pattern (Transition Density = 80%) -15 101 102 103 104 105 Modulation Frequency [Hz] 106 107 108 Bit Synchronization Time 4000 3500 C1 = 0.01F, R1 = 4.7k, Ta = 27C Pattern: Fibre Channel ldle Pattern (Transition Density = 80%) 3000 Bit Synchronization Time [ns] 2500 2000 1500 1000 500 0 51.5 52 52.5 REFCLK [MHZ] 53 53.5 54 - 12 - CXB1585N Example of Random jitter measurement (Retimed data 1.0625Gbps) [100mV/div] C1 = 0.01F, R1 = 4.7k, Ta = 27C SDIN: Fibre Channel ldle Pattern (Transition Density = 80%) RJ = 9.6ps (RMS) [50ps/div] Eye pattern (Retimed data 1.0625Gbps) [200mV/div] C1 = 0.01F, R1 = 4.7k, Ta = 27C SDIN: Fibre Channel ldle Pattern (Transition Density = 80%) [200ps/div] - 13 - CXB1585N Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 - 0.1 7.8 0.1 0.1 13 24 A 1 + 0.1 0.22 - 0.05 12 + 0.05 0.15 - 0.02 0.65 0.1 0.1 0.13 M 5.6 0.1 0 to 10 NOTE: "" Dimensions do not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-24P-L01 SSOP024-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g - 14 - 0.5 0.2 7.6 0.2 |
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